Spectrum +3 Gate Array... - Page 1 (2024)

Speccy_Pete wrote: ↑Wed Jul 21, 2021 5:47 pmIf someone was silly enough to want to remove the gate array from a +3, could you in theory replace it with individual ic's so that part of the circuit was for instance the same as the grey +2?

I've not hardware skills, so not sure, but look here:
https://www.secarica.ro/index.php/en/zx ... 3s-project

spider wrote: ↑Thu Jul 22, 2021 9:08 am

Speccy_Pete wrote: ↑Thu Jul 22, 2021 8:13 amThat'll teach me to reply when I'm half asleep...

I'm sure there's been many a 'magic smoke trick' or popping noise from a mistook or two when not being fully awake with the job in question.

Regarding what I said about protoyping I guess you'd end up with something like this , well kind of:

I was half right, some of the tap points I mentioned on IC6 are connected to IC15 on the Grey +2, but yes... I may have let the magic smoke escape on more than one occasion trying to finish something when I should have stopped due to being half a sleep!

I hope it wouldn't end up that big I'd never fit it back in the original case!?!

+3code wrote: ↑Thu Jul 22, 2021 9:49 amI've not hardware skills, so not sure, but look here:
https://www.secarica.ro/index.php/en/zx ... 3s-project

Appreciate the reply and link, I'll have a look!

That +3 project looks fun in some ways, also much work

[mention]Speccy_Pete[/mention] , no I doubt it would fit into the original case , maybe into a desk

Does remind me I gave away a couple of years ago an empty Dragon32 case, had keyboard but no 'main pcb' , I had a vague idea of putting a ZX81 into it as the keyboard was quite nice. Anyway all in the past now.

Andy.

The Jetset Willy and Manic Miner community

Speccy_Pete wrote: ↑Thu Jul 22, 2021 2:02 amIs there anywhere on the +3 you can tap into the BANK Switching, Paging and VRAM or is it all done internally with the gate array?

To what end?
You could work out what chip is paged by tapping the address lines to the RAM and ROM chips, but it's easier to just hook some logic up to the expansion port to mirror the paging registers.

My rubbish website including the redrawn Amstrad schematics and the Sinclair Wiki.

Guesser wrote: ↑Thu Jul 22, 2021 11:14 amTo what end?
You could work out what chip is paged by tapping the address lines to the RAM and ROM chips, but it's easier to just hook some logic up to the expansion port to mirror the paging registers.

Nothing crazy, I'd like a simple visual indicator...

Like this HERE

My rubbish website including the redrawn Amstrad schematics and the Sinclair Wiki.

Guesser wrote: ↑Thu Jul 22, 2021 12:03 pmOh right. In that case you could definitely do that with a plug-in expansion, or CPU passthrough PCB.

Just to be awkward I'd need it fitting internally... but cannot use a CPU passthrough as It will eventually have one fitted for internal IDE

Reason I asked about tapping onto another IC like IC6 on the +2.

My rubbish website including the redrawn Amstrad schematics and the Sinclair Wiki.

Guesser wrote: ↑Thu Jul 22, 2021 12:31 pmWell you could tap the buses elsewhere, but it would just get really messy. If you were making a PCB to decode the paging ports and drive LEDs you could put an IDE header in it

Yea, would rather not have wires running all over the place!

Nice and easy on the +2 IC6... tap the pins away you go... managing the wiring wasn't hard either.

Hmmm, something to think about.

The functions provided by IC6 (74LS174) are all part of the gate array in a +2A, +2B or +3.
For the ROM bank, you can still pick up the relevant address line.

But using the address lines for the DRAM chips is more tricky, as they use a multiplexed address bus (*) so would need logic to demultiplex the address lines. But now it’s getting rather complex…

* Eight lines carry a sixteen bit address, the first eight bits of the address are presented to the DRAM chips and then latched in with the /RAS strobe signal, then the remaining eight bits latched in with the /CAS strobe signal.

As guesser says, it’s just as easy to add a programmable logic chip to carry out the functions of IC6 in a grey +2.

Mark

1024MAK wrote: ↑Thu Jul 22, 2021 1:31 pmThe functions provided by IC6 (74LS174) are all part of the gate array in a +2A, +2B or +3.
For the ROM bank, you can still pick up the relevant address line.

But using the address lines for the DRAM chips is more tricky, as they use a multiplexed address bus (*) so would need logic to demultiplex the address lines. But now it’s getting rather complex…

* Eight lines carry a sixteen bit address, the first eight bits of the address are presented to the DRAM chips and then latched in with the /RAS strobe signal, then the remaining eight bits latched in with the /CAS strobe signal.

As guesser says, it’s just as easy to add a programmable logic chip to carry out the functions of IC6 in a grey +2.

Mark

Yep, I figured understood the gate array was doing the function of IC6 as well as a couple of other IC chips from the original +2 design...

The rest is beyond my abilities unfortunately...

I just about understand enough to follow a How2 someone has generously made public, but...

I wouldn't have a clue how or where to start doing it all myself though.

Appreciate the reply and extra info Mark!